Experience: 8+ Years
Domain: Analog/Mixed-Signal (AMS) Verification
Role Overview
We are looking for an experienced AMS Verification Lead with strong hands-on expertise in Analog/Mixed-Signal verification, SystemVerilog, UVM, and Real Number Modeling (RNM). The ideal candidate will lead end-to-end verification of mixed-signal IPs, develop robust verification environments, drive coverage closure, and ensure verification quality and sign-off.
Key Responsibilities
Lead end-to-end verification of analog and mixed-signal IPs.
Develop verification plans, test strategies, testbenches, and verification methodologies.
Build and maintain SystemVerilog/UVM-based verification environments.
Develop, integrate, and validate Real Number Models (RNM) for analog blocks.
Verify interactions between analog and digital components in mixed-signal designs.
Perform functional coverage analysis, debug simulation failures, and drive coverage closure.
Verify mixed-signal IPs such as ADCs, DACs, PLLs, oscillators, and LDOs.
Manage regression execution, verification schedules, technical deliverables, and sign-off.
Collaborate with analog design, digital design, and SoC verification teams.
Mentor verification engineers and provide technical leadership.
Must-Have Skills
8+ years of relevant semiconductor verification experience preferred.
Strong hands-on experience in Analog/Mixed-Signal (AMS) verification.
Proficiency in SystemVerilog and UVM.
Practical experience with Real Number Modeling (RNM) and mixed-signal verification methodologies.
Experience in analog-digital interface verification.
Strong debugging, functional coverage, regression management, and verification sign-off skills.
Experience taking ownership of verification activities and technical deliverables.
Good-to-Have Skills
Experience with Cadence Virtuoso, AMS Designer, or equivalent AMS simulation tools.
Knowledge of analog behavioral modeling and SystemVerilog-AMS.
Experience verifying ADCs, DACs, PLLs, oscillators, LDOs, or similar mixed-signal IPs.
Experience in semiconductor IP or SoC-level verification.
Python or Tcl scripting for verification automation.
Prior experience mentoring engineers or leading verification teams.
Ideal Candidate
A hands-on AMS Verification Lead with strong expertise in SystemVerilog, UVM, and RNM, along with proven experience in mixed-signal IP verification, verification planning, debugging, coverage closure, and sign-off.
Candidates should demonstrate practical AMS verification experience rather than digital-only Design Verification or analog circuit design experience.