Tsavorite Scalable Intelligence
Website:
tsavoritesi.com
Job details:
Principal Design Verification Engineer: SOC Focused [Experience Level 14+]
Bangalore
Founded in 2023,by Industry veterans HQ in California,US
Location: Greater Bengaluru Area
Company Description
We are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI.
Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.Principal Design Verification Engineer: SOC Focused [Experience Level 10+]Senior Design Verification Engineer: SOC Focused [Experience Level 10+]
Job Description
We are seeking a SoC Verification Engineer to work on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels. This is full-chip, cross-IP, real-silicon mindset verification.
Senior Design Verification Engineer: SOC Focused [Experience Level 14+]
Job Description
We are seeking a SoC Verification Engineer to work on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels. This is full-chip, cross-IP, real-silicon mindset verification.
Key Responsibilities
- Validate cache coherency across multiple cores, agents, accelerators, across chip boundaries
- Execute SoC-level DV plans for flows pertaining Cache Coherency and involving ARM complexes in the flow path.
- Implement system level stimulus for concurrent core/cache/dma/io traffic paths
- Coherency across chip boundaries
- Scalability testing:
- N-chip configurations
- Implement:
- UVM-based system tests including mid-transaction reset, contention scenario
- Scoreboards and data integrity checks under high throughput, concurrent traffic
- Debug complex failures using:
- Waveforms
- Transaction traces
- Firmware interaction
- Collaborate with RTL, architecture, and firmware teams
Required Skills & Experience
- Experience verifying ARM-based SoCs
- Understanding of cache coherency (CHI / ACE preferred)
- Proficiency in:
- SystemVerilog / UVM
- Transaction-level verification
- Solid grasp of:
- AXI / NoC architectures
- DMA engines and memory systems
Preferred Qualifications
- Multi-chip / chiplet system experience
- Exposure to real workloads (storage, networking, AI accelerators)
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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