Texas Instruments
Website:
ti.com
Job details:
🏢 About Texas Instruments
Texas Instruments (TI) is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips. Our products power everything from industrial automation to automotive safety systems, enabling engineers and innovators worldwide to create smarter, more efficient technology.
👥 About the Team — High Speed Data Interface Product Group
The High Speed Data Interface product group focuses on the development of differentiated high-speed SerDes SoCs targeted for automotive and industrial markets. There are two primary focus areas — Ethernet PHY and FPD-Link.
Ethernet PHY Group: Ethernet PHY applications target Industrial, Robotics, and Automotive applications in control and radar sensor aggregation space using standard-compliant devices. A large number of applications — like in-vehicle driver alertness monitors, steering, or accelerator control in automotive and robotic applications — require an Ethernet interface. The ubiquity of Ethernet-enabled devices allows customers to simplify connecting large numbers of devices in automotive and robotic environments.
Customers expect robust performance in the presence of interference and electrostatic discharge (ESD) events, along with processing offload capabilities to simplify their design. The low-cost migration of control applications from CAN to Ethernet presents unique challenges — requiring interdisciplinary skills to work on trade-offs in analog/digital realization with aggressive cost and power targets.
FPD-Link Group: The proprietary FPD-Link interface addresses multi-gigabit (up to 20 Gbps) automotive and industrial sensor and display markets. The constant increase in the density of electronic sensing and display content in automotive and robotics, along with application complexity, is pushing data rate (>20 Gbps) and Bit Error Rate (BER) performance requirements higher.
Due to automotive functional safety requirements, customers demand robust performance at these high data rates under challenging automotive environments. At the same time, low power consumption is a key customer requirement — making successful product design a true multi-domain engineering challenge.
The Broader Mission: As part of this product group, you will be engaged in designing solutions that span Analog, Digital, and Signal Processing domains to mitigate impairments such as high channel loss (due to long cable reach), ESD strikes, and narrowband interference. The team implements high-performance equalization circuits (CTLE, FFE, DFE), high-speed converters (DAC, ADC), high-speed digital front-ends, signal processing algorithms, embedded microcontrollers, and high-speed interfaces for camera and display systems.
The team has successfully achieved several differentiated innovations through collaborative, cross-domain optimization. Many challenging problems remain open for investigation for next-generation devices.
🌟 The entire product lifecycle — spanning product specification to customer and application support — is owned by the product group located in Bangalore, giving each team member tremendous learning opportunity and enhanced scope to influence the global success of the product.
We are looking for passionate, creative, and self-driven engineers who challenge traditional techniques and come up with innovative solutions to make a difference.
🎯 Role Overview
As a Physical Design & Implementation Engineer, you will be at the heart of converting architectural intent into high-performance silicon. You will own the physical realization of complex mixed-signal SerDes SoCs — ensuring that aggressive performance, power, and area targets are met for automotive and industrial deployment. Your work directly determines whether cutting-edge algorithms and circuits designed by your colleagues successfully translate into a robust, manufacturable chip.
🔧 Key Responsibilities
- Floorplanning: Define and execute optimal floorplans for complex mixed-signal SoCs, carefully partitioning analog and digital domains to meet performance, signal integrity, and power targets
- Place & Route (PnR): Lead full-chip and block-level place-and-route for multi-gigabit SerDes designs operating under stringent timing, power, and area constraints
- Timing Closure: Drive multi-corner, multi-mode (MCMM) timing closure using industry-standard Static Timing Analysis (STA) tools, resolving setup, hold, and clock domain crossing (CDC) violations
- Power Optimization: Design and validate robust power distribution networks (PDN); manage IR drop and electromigration (EM) to meet automotive-grade reliability standards
- Clock Tree Synthesis (CTS): Implement and optimize clock trees to minimize skew, latency, and power consumption across high-speed SoC domains
- Physical Verification: Own DRC, LVS, and ERC sign-off; manage antenna violation fixes and ensure tapeout-readiness
- Cross-functional Collaboration: Work closely with analog layout engineers, RTL designers, and verification teams for seamless top-level integration and interface optimization
- Feedback Loop: Provide timing-aware and layout-aware feedback to RTL and circuit design teams for design-for-implementation (DFI) improvements
- Tapeout Readiness: Coordinate all physical implementation deliverables for chip tapeout, including final GDS, netlist, and signoff reports
✅ Required Qualifications
- Education: B.Tech / M.Tech in VLSI / Electronics / Electrical Engineering
- Experience: 3–5 years of hands-on physical design experience on high-speed, high-complexity SoCs
- Strong proficiency in industry-standard PnR tools — Synopsys IC Compiler II (ICC2) and/or Cadence Innovus
- Solid understanding of Static Timing Analysis (STA) using Synopsys PrimeTime or equivalent
- Demonstrated experience with timing closure techniques: useful skew, multi-cycle paths, clock gating
- Working knowledge of power analysis and optimization — dynamic and static power, IR drop (Redhawk/Voltus)
- Hands-on experience with DRC/LVS sign-off tools (Mentor Calibre, Synopsys ICV)
- Understanding of deep submicron process effects: electromigration, antenna, double patterning
- Familiarity with scripting using TCL / Python for flow automation and custom checks
🌟 Preferred / Good-to-Have Skills
- Experience in mixed-signal SoC physical design — integrating analog IP with high-speed digital domains
- Exposure to high-speed SerDes physical design constraints (signal isolation, shielding, analog proximity rules)
- Knowledge of automotive-grade design requirements (AEC-Q100, ISO 26262 layout guidelines)
- Experience with low-power design techniques: multi-voltage domains, power gating, retention flops
- Exposure to advanced nodes (16nm, 12nm, 7nm FinFET or below)
- Track record of successfully contributing to tapeout on production-grade SoCs
💡 What Makes This Role Unique
🚗 Domain Impact Your silicon goes into automotive safety & perception systems globally
🔄 Full Lifecycle Ownership Spec → Silicon → Customer — all from Bangalore
🤝 Cross-Domain Collaboration Work alongside analog, digital, DSP & firmware engineers
🌍 Global Influence Shape products deployed in automotive platforms worldwide
🧠 Innovation Culture Differentiated, award-winning innovations
📈 Career Growth High-visibility role with direct impact on product success
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