IBM Global Financing
Website:
ibm.com
Job details:
Introduction
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Your Role And Responsibilities
- Develop and implement low-power design techniques for digital IC/SoC designs.
- Define and execute power intent using UPF/CPF methodologies.
- Proficiency in low-power checking tools like CLP, VCLP
- Perform power analysis, optimization, and debugging across RTL, gate-level, and physical design stages.
- Collaborate with architecture and RTL teams to identify power-saving opportunities.
- Analyze dynamic and leakage power and recommend design improvements.
- Work with synthesis and physical design teams for clock gating, power gating, multi-voltage, and DVFS implementation.
- Support low-power verification flows including simulation and formal verification.
- Review and debug power-related issues during chip integration and signoff.
- Develop scripts and automation for power analysis and reporting.
- Ensure designs meet power, performance, and area (PPA) targets.
Preferred Education
Master's Degree
Required Technical And Professional Expertise
- Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, VLSI Design, or related field.
- 7+ years of experience in low-power digital design or SoC development.
- Strong understanding of CMOS fundamentals and power optimization techniques.
- Experience with UPF/CPF and low-power verification methodologies.
- Familiarity with ASIC/SoC design flow from RTL to GDSII.
- Hands-on experience with EDA tools such as:
- Synopsys (Design Compiler, PrimePower, CLP, VCLP)
- Cadence (Genus, Innovus, Joules)
- Siemens/Mentor low-power tools
- Good knowledge of clock gating, power gating, retention, isolation, and voltage islands.
- Proficiency in Verilog/SystemVerilog and scripting languages such as Tcl, Python, or Perl.
Preferred Technical And Professional Experience
- Experience with advanced technology nodes (7nm, 5nm, 3nm).
- Knowledge of DVFS and multi-power domain architectures.
- Exposure to STA, physical design, and DFT concepts.
- Familiarity with AI/ML accelerator or mobile SoC power optimization.
- Strong debugging and problem-solving skills.
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