Physical Design EngineerNoida Institute of Engineering & Technologyfull-timeRequired skillsPythoncompilerGatePerlTCLAbout the role Website: niet.co.in Job details: Floorplanning & Partitioning: Design the silicon die map, establishing physical boundaries, power grids, and pin placements.Placement & Routing (PnR): Utilize EDA tools to place standard cells and macros, routing millions of connections while managing congestion.Clock Tree Synthesis (CTS): Design clock distribution networks to minimize clock skew across the chip.Static Timing Analysis (STA): Perform exhaustive timing analysis to eliminate setup and hold violations, ensuring the chip meets speed targets.Physical Verification: Ensure the layout follows foundry Design Rule Constraints (DRC), Layout vs. Schematic (LVS), and resolves issues like antenna effects.Power Optimization: Implement power-saving techniques like voltage scaling and clock gating to reduce power consumption and resolve voltage (IR) drops.EDA Tools Proficiency: Mastery of Cadence Design Systems (Innovus) or Synopsys (IC Compiler II, PrimeTime) software suites.Scripting Languages: Strong proficiency in Tcl, Perl, or Python for design automation and flow development.Hardware Description Languages (HDLs): Solid understanding of Verilog or SystemVerilog.CMOS & Semiconductor Physics: Deep knowledge of CMOS logic, transistor characteristics, and the constraints of advanced fabrication nodes.Education: Bachelor’s or Master's degree in Electrical Engineering, Electronics, or Computer Science.Experience: Ranges from entry-level (fresher) to senior roles with experience taping out multi-million gate designs across sub-micron to advanced nanometer process nodes. Click on Apply to know more. This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.