Website:
corpmatch.in
Job details:
Company Description Corp Match Private Limited (Corpmatch) is a placement-focused training and hiring ecosystem that prepares students to become industry-ready professionals. The company collaborates with colleges, universities, and corporate partners to align academic learning with real-world business expectations and measurable placement outcomes. Through structured programs in IT and non-IT skills, financial domain specialization, corporate readiness, and industry-aligned certifications, Corpmatch supports sustainable talent pipelines across India. Its mission is to reduce the skill gap, improve employability, and create meaningful career opportunities for learners. Corpmatch works closely with institutions and companies to deliver trained, reliable talent while helping students accelerate their careers.
Role Description The Physical Design Engineer will work full time on-site at the Bengaluru location, focusing on backend VLSI design implementation from RTL to GDSII. Day-to-day responsibilities include floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure for complex digital designs. The role involves collaborating with front-end design, verification, and DFT teams to resolve design issues, optimize performance, power, and area, and ensure sign-off for tape-out using industry-standard EDA tools. The engineer will perform static timing analysis, physical verification (DRC/LVS), signal integrity checks, and ECO implementation, while documenting design flows and maintaining best practices. The position requires working in a fast-paced environment, contributing to project reviews, and supporting continuous improvement of physical design methodologies.
Qualifications
- Strong physical design fundamentals, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
- Proficiency with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor) for STA, physical verification, and power analysis.
- Solid understanding of digital design concepts, ASIC/SoC flow, and RTL-to-GDSII implementation.
- Knowledge of static timing analysis, signal integrity, IR drop, electromigration, and low-power design techniques.
- Experience with DRC/LVS sign-off, ECO flows, and design for manufacturability is an advantage.
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field.
- Strong analytical, problem-solving, and debugging skills with attention to detail.
- Ability to collaborate effectively in cross-functional teams and communicate technical concepts clearly.
- Willingness to learn new tools and methodologies and adapt to evolving project requirements.
Click on Apply to know more.