Chiplogic Technologies
Website:
chiplogictech.com
Job details:
Company Description
Established in 2018, Chiplogic Technologies (Chiplogic) is an IP and Product Engineering Services company specializing in Semiconductor, Systems, IoT, and AI/ML domains. Chiplogic delivers high-quality and reliable services, including turnkey semiconductor design and system solutions, from concept to silicon. The company also focuses on AI/ML services through its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, providing innovative solutions for real-world applications.
Role Description
We are looking for an experienced Senior Physical Design Engineer / Lead with strong expertise in low-power multi-voltage SoC implementation. The candidate should have hands-on experience driving complete physical design execution from floorplanning to signoff convergence for complex SoCs.
Key Responsibilities
- Lead Physical Design execution of low-power, multiple voltage/power domain based SoCs
- Handle:
- Die-size estimation
- IO/ESD/package planning
- Floorplanning
- Power planning
- Drive complete backend implementation flow including:
- Synthesis
- Place & Route
- STA/timing closure
- Physical Verification
- IR/EM convergence
- Perform LP-aware synthesis and optimize flow to achieve PPA (Power, Performance, Area) targets
- Debug and resolve:
- RTL2Netlist LEC issues
- Netlist-to-Netlist LEC issues
- LP-LEC issues
- Run CLP checks and resolve gate-level CLP violations
- Work on multi-voltage and multi-power domain low-power implementation methodologies
- Develop and maintain automation using:
- Tcl scripting
- Makefile-based flows
Required Skills
- Strong expertise in:
- Low Power SoC Physical Design
- Multi-voltage / multi-power domain implementation
- Synthesis and timing closure
- IR/EM analysis and convergence
- Physical verification signoff
- Expert knowledge of:
- Cadence Innovus
- Cadence Genus
- Cadence Tempus
- Cadence CLP
- Cadence LEC
- Siemens Calibre
- Ansys RedHawk-SC
- Strong understanding of:
- UPF/CPF concepts
- Low power methodologies
- STA concepts
- Physical verification flows
- Experience with:
- Tcl automation
- Unix/Linux environment
- Makefile-based flows
Preferred Qualifications
- Bachelor’s/Master’s degree in Electronics/VLSI/Microelectronics
- Experience in handling complex SoC designs at advanced technology nodes is preferred
- Strong debugging and problem-solving skills
- Excellent communication and team collaboration abilities
Experience
- 6+ Years (can be adjusted based on requirement)
Location
Notice Period Preference
- Immediate joiners / candidates serving notice period preferred.
Click on Apply to know more.