Senior ASIC Design Engineer
Palo Alto Networks
- Salary
- $156k - $253k
- Experience
- 10+ yrs
- Location
- Santa Clara, California, United States
- Job type
- Full-time
Required skills
- SystemVerilog
- Python
- C++
- Perl
- bash
- tcsh
- PCIe
- Ethernet
- DDR
About the role
BS in EE, CE, or CS; 10+ years front-end ASIC design ownership; expert SystemVerilog RTL; experience with high-speed interfaces (PCIe, Ethernet, DDR); scripting proficiency in Python, C/C++, Perl, bash or tcsh.
About Palo Alto Networks
Global cybersecurity platform providing network, cloud, and AI-driven security solutions.
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