UST
Website:
ust.com
Job details:
Hi,
Please find the JD below.
FPGA Verification, 4 to 7 years of experience.
- Develop and implement verification plans for FPGA designs.
- Design and maintain testbenches for FPGA projects.
- Conduct functional simulations and analyze results.
- Collaborate with design engineers to understand design intent and constraints.
- Document verification processes and results.
- Identify, debug, and resolve issues found during verification.
- Stay up-to-date with industry best practices in FPGA verification.
Please share your resume to jayalakshmi.r2@ust.com
Regards,
Jaya
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