Principal Engineer - HBM SOC Physical Design - TPG

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Our ultimate goal is to deliver the lowest power per bit solutions in the industry! Position Overview: Micron is hiring a Principal Engineer - HBM SOC Physical Design! You will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful Responsibilities: Completing various tasks in the netlist to GDSII implementation for partition(s), meeting schedule, and design goals. Collaborating with the Architect, Front End Design, and CAD teams to deliver best-in-class designs. Assisting Front End Design and Integration Engineers with SRAM/RF specification and synthesis design constraints. Resolving and improving design and flow issues related to physical design, identifying potential solutions, and working with CAD teams as needed. Debugging and identifying root causes and solutions for netlist timing issues or post-silicon timing issues. Required Qualifications: BSEE with 10+ years of relevant experience. 10+ years of technical expertise in one or more areas: Physical Synthesis, Floor-Planning, Place and Route, Power Grid, Clock Tree Synthesis, Constraint Development with RTL engineers, Static Timing Analysis for Partition Level and Full Chip Level Timing Closure, SRAM Compilers, Physical Design Verification (DRC/LVS), EMIR, Formal Equivalence Verification (FEV) 2+ years of experience in Unified Power Format (UPF) for describing power intent. Excellent knowledge of Synthesis Design Constraints and Static Timing Analysis. Excellent understanding of clocking concepts, including asynchronous crossings and structures used to synchronize clock domain crossings.. Preferred Qualifications: MSEE or higher. 1+ years of experience with DRAM implementation and JEDEC specifications, preferably with the HBM product family. 3+ years of experience in scripting languages such as TCL/ Python. 2+ years of experience in implementing any of the following focus areas: memory array architectures, on-die and off-die high-speed signaling, PHY & interface development, power delivery network planning and optimization, power consumption reduction, CMOS requirements identification, packaging technologies, and thermal modeling. Good verbal and written communication skills with the ability to efficiently synthesize and convey sophisticated technical concepts to other partners and leadership.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.