ASIC Engineer, Implementation - Timing
Meta
- Salary
- $114k - $172k
- Experience
- 2+ yrs
- Location
- Sunnyvale or Austin
- Job type
- Full-time
Required skills
- PrimeTime
- Python
- Tcl
- Perl
- SystemVerilog
About the role
Bachelor's degree in Computer Science, Computer Engineering, or equivalent; 2+ years ASIC implementation with static timing analysis and timing closure; experience with PrimeTime, SDC constraints, logic synthesis, and scripting in Python, Tcl, or Perl.
About Meta
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