UANDWE, Inc.
Website:
uandwe.com
Job details:
Memory Layout
- Role: Layout Design of SRAM/CAM/RF compiler memories in 2/3/4/5nm technology.
- Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories.
- Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required
- Experience : 3 to 12 Years
Looking for the following expertise:
1. Understanding of memory architecture
2. Experience in creating basic memory layouts from scratch
3. Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers
4. Knowledge of compiler issues
5. Understanding of reliability issues
6. Simulation effects
7. EMI (Electromagnetic Interference) considerations
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