Ambit Semiconductors Private Limited
Website:
ambitsemi.com
Job details:
Job Overview
We are seeking a Hands-on experience with Calibre, Synopsys ICV, Cadence Virtuoso, or equivalent layout tools. Knowledge of advanced CMOS technologies (FinFET nodes preferred). Good understanding of EM/IR, DFM, power integrity, and tapeout flows. Strong debugging, problem-solving, and communication skills
Key Responsibilities
Own the complete custom layout of SRAM bitcell arrays, memory peripherals, test structures, and memory macros in advanced CMOS technologies. Develop and optimize memory floorplans, including array layout, peripheral placement, power grid design, routing channels, and macro assembly. Perform and debug DRC, LVS, ERC, Antenna and physical verification using Calibre, ICV, or equivalent tools. Support EM/IR analysis, power integrity, DFM, density fill, dummy fill, and layout-dependent effects (LDE) for successful tapeout. Collaborate with circuit designers to convert schematics into high-quality layouts, ensuring matching, symmetry, shielding, parasitic, and reliability requirements. Work closely with PnR, CAD, Integration, and Foundry teams to resolve top-level layout and integration challenges.
Drive layout methodologies, reusable practices, and quality improvements while mentoring junior engineers.
Required Skills
Strong experience in Memory Layout / SRAM Layout / Custom Layout. Expertise in DRC, LVS, ERC, Antenna checks, and physical verification. Hands-on experience with Calibre, Synopsys ICV, Cadence Virtuoso, or equivalent layout tools. Knowledge of advanced CMOS technologies (FinFET nodes preferred).
Good understanding of EM/IR, DFM, power integrity, and tapeout flows. Strong debugging, problem-solving, and communication skillsExample: Excellent verbal and written communication skills
Click on Apply to know more.