Website:
siliconboard.co
Job details:
About the job
Job: Memory Layout Design Engineer
Employment Type: Full-time
Experience: 5–10 years
Function: Semiconductor Engineering — Memory Design
About SiliconBoard
SiliconBoard connects semiconductor engineering talent with companies across the semiconductor ecosystem.
This opportunity is offered through the SiliconBoard Talent Network. Shortlisted profiles are reviewed and shared with relevant hiring companies within our partner network.
About the Role
We are looking for Memory Design Engineers with 5–10 years of hands-on experience in custom memory circuit design and development.
The role involves design, simulation, optimization, and characterization of embedded memory blocks such as SRAMs, register files, ROMs, and related memory structures.
You will work across memory architecture, bitcell and peripheral circuit design, PVT validation, post-layout verification, and design closure.
Key Responsibilities
Memory Circuit Design
- Design and optimize SRAM, register file, ROM, or related embedded memory circuits.
- Work on bitcells and memory peripheral circuits.
- Design sense amplifiers, write drivers, precharge circuits, decoders, word-line drivers, and control logic.
- Optimize circuits for speed, power, area, stability, and yield.
- Evaluate design trade-offs across different memory architectures.
Memory Architecture
- Understand memory specifications including size, aspect ratio, frequency, voltage, and power targets.
- Define or support array architecture and banking strategies.
- Work on row and column architecture, multiplexing, and peripheral organization.
- Support low-power and high-performance memory architectures.
Simulation and Verification
- Perform DC, transient, noise, and statistical simulations.
- Verify functionality across process, voltage, and temperature corners.
- Perform Monte Carlo and mismatch analysis.
- Analyze read stability, writeability, access time, leakage, and dynamic power.
- Debug functional and performance issues at circuit level.
Design Optimization
- Optimize memory designs for PPA targets.
- Work on low-voltage and high-frequency design challenges.
- Analyze critical read and write paths.
- Improve robustness against process variation and device mismatch.
- Support design margin analysis and yield improvement.
Required Qualifications
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
- 5–10 years of industry experience in memory circuit design.
- Strong understanding of CMOS circuit design and semiconductor devices.
- Hands-on experience with SRAM or other embedded memory architectures.
- Experience designing memory peripheral circuits.
- Strong knowledge of read and write operation, stability, and timing.
- Experience with PVT and Monte Carlo analysis.
- Experience with transistor-level simulation.
- Understanding of layout-dependent effects and parasitics.
- Ability to debug circuit-level performance issues.
Preferred Qualifications
Relevant experience in one or more of the following areas:
- SRAM design
- Register file design
- ROM design
- Cache memory circuits
- SRAM bitcell design
- Sense amplifier design
- Write driver design
- Row and column decoder design
- Word-line driver design
- Precharge and equalization circuits
- Memory timing and control circuits
- Low-voltage memory design
- High-speed memory design
- Low-power memory design
- Memory characterization
- Memory compiler development
- Redundancy and repair
- Yield optimization
- Advanced process-node memory design
- Post-layout simulation
- Silicon characterization
- Multiple tapeouts
Tools
Experience with relevant industry-standard tools is preferred, including:
- Cadence Virtuoso
- Cadence Spectre
- Synopsys HSPICE
- SPICE-based simulation environments
- Monte Carlo and statistical analysis tools
- Physical verification and extraction tools such as Calibre or equivalent
Hiring Process
- Submit your resume through the application link.
- Profiles are reviewed and shortlisted by the SiliconBoard team.
- Shortlisted candidates may receive a technical screening or AI-based technical interview.
- Qualified profiles are shared with the hiring company for further evaluation.
Additional Information
This opportunity is with a SiliconBoard client company and not with SiliconBoard directly.
Compensation is determined by the hiring company based on experience, technical depth, role requirements, and interview performance.
Submission of an application does not guarantee an interview, referral, or employment.
Profiles are evaluated based on memory architecture experience, circuit ownership, SRAM depth, peripheral circuit design, process-node experience, PVT and Monte Carlo analysis, post-layout closure, characterization, tapeout experience, and the requirements of the hiring company.
Click on Apply to know more.
