Magma Design Automation
Website:
synopsys.com
Job details:
Memory Compiler Design– Sr. Architect
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent two decades building memory architectures that actually ship in silicon, not just pass reviews. You know that the difference between an SRAM compiler that gets adopted and one that gets worked around is usually in the decisions you made about PPA tradeoffs six months before tapeout, and you are the kind of architect who sees those decisions coming. You have debugged enough Hspice decks at 2am to know that elegant circuit design beats clever hacks every time, and you have mentored enough engineers to know that teaching someone to see the problem is worth more than handing them the answer.
You do not need a perfect spec to start architecting. You ask the right questions, map the constraints, and find a path that balances performance, area, and power without sacrificing one for the others. You have built compilers for SRAM, register files, ROM, TCAM, and you understand not just how they work but why certain topologies win in certain process nodes. At Synopsys, you will shape the next generation of memory IP that powers everything from AI accelerators to automotive SoCs, and the team you work with will expect you to lead, not just contribute.
What You'll Be Doing
- Architect and develop memory compiler IP across SRAM, register file, ROM, and TCAM technologies, owning the full flow from circuit design through functional verification and signoff
- Design and optimize analog circuits at the transistor level using Hspice/XA, balancing PPA for advanced process nodes and customer-specific requirements
- Build and refine memory compiler flows using Python, automating design generation, verification, and characterization to improve turnaround time and design quality
- Collaborate with product engineering, verification, and customer support teams to align compiler features with market requirements and resolve complex design issues
- Drive functional verification using industry-standard tools, ensuring correctness across process corners, voltage ranges, and operating conditions before customer delivery
- Mentor engineers across circuit design, memory architecture, and compiler methodology, raising the technical bar for the entire team
- Contribute to technical roadmaps and architecture decisions that define the next generation of Synopsys memory IP offerings
The Impact You Will Have
- Deliver best-in-class memory compilers that become the foundation for customer SoCs across AI, automotive, mobile, and high-performance computing markets
- Reduce time-to-market for Synopsys customers by building compiler flows that are faster, more reliable, and easier to integrate than alternatives
- Solve PPA challenges that unlock new use cases for embedded memory in advanced nodes where traditional approaches fail
- Elevate the technical capability of the engineering team through hands-on mentorship, design reviews, and knowledge sharing that sticks
- Shape the technical direction of Synopsys memory IP by bringing deep expertise to architecture discussions and product planning
- Enable successful customer tapeouts by delivering memory compilers that meet aggressive performance, area, and power targets on schedule
- Build a culture of rigor and excellence where circuit quality, verification coverage, and design robustness are non-negotiable
What You'll Need
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field
- 20+ years of hands-on experience designing embedded memory IP including SRAM, register files, ROM, or TCAM, with deep expertise in circuit-level design and functional verification
- Proven experience building or working within memory compiler flows, from architecture definition through automated design generation and signoff
- Strong proficiency in Python for scripting, automation, and flow development
- Expert-level skill in Hspice or XA for analog circuit simulation, optimization, and characterization
- Solid understanding of industry-standard verification tools and signoff flows for memory IP
- Experience with advanced process nodes (7nm and below) is a strong plus
Who You Are
- You can walk into a technical review, see the flaw in a bitcell design or compiler flow, and explain the fix in a way that makes the team want to implement it
- You have strong opinions on memory architecture, but you listen first and change your mind when the data says you should
- You are organized enough to manage multiple compiler development efforts in parallel without losing track of quality or schedule
- You do not wait for someone else to solve the hard problem, if the circuit is not converging or the flow is breaking, you dig in and fix it
- You treat mentorship as part of the job, not an extra, and you measure your success by how much the engineers around you grow
- You communicate complex tradeoffs clearly to stakeholders across engineering, product management, and customer-facing teams without losing the technical nuance
The Team You'll Be Part Of
You will be part of a dynamic and innovative engineering team at the forefront of high-performance silicon chip and software development. Our team relentlessly pushes technology boundaries, delivering solutions that drive the Era of Pervasive Intelligence. We collaborate closely to ensure our products meet the highest standards of quality and performance.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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