Senior Digital Verification Engineer

MaxLinear

Experience: 4+ yrs
Location: Bangalore, Karnataka, India
Job type: Full-time

Required skills

SystemVerilog
UVM
Verilog-A
Verilog-AMS
Perl
Python

About the role

Bachelor's in Electrical/Electronics/Computer Engineering with 4+ years experience or Master's with 2+ years; SystemVerilog, UVM, constrained random, assertions, functional coverage; ASIC verification experience; strong analytical and communication skills.

About MaxLinear

Public fabless semiconductor design company serving broadband, mobile, wireline, data-center, and industrial customers with communications SoCs.

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