About the role
Basic Requirements:
Hands-on experience in RTL design and verification using Verilog/System Verilog and front-end design/verification tools & flows
Ability to work with a team of hardware and software engineers to define and implement the high-level architecture
Deliver RTL Design and Coding for various sections of an SoC and related logic
Work on IP development using standard coding guidelines.
Experience:
Experience working with the physical design team and awareness of physical design requirements
Familiarity with Synopsys EDA tools & FPGA prototyping
Knowledge of AMBA protocol, PCIE, and DDR, and VLSI design flow
Strong knowledge of IP/SOC design methodologies
About the company
Manjeera Digital Systems Pvt Ltd.
Unit B-1002,
10th floor, B-Block, The Platina, Gachibowli,
Hyderabad, Telangana- 500032, India.
+91-9391000206 (India)
+91-9392447307 (India)
+91-9391000208 (India)
+1 408 205 7710 (USA)
info@manjeerads.com
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