Website:
fermions.co
Job details:
About Fermions
Fermions ASI is a deep-tech startup developing advanced AI systems for digital semiconductor design. We are tackling a fundamental problem: Can AI generate correct, synthesizable hardware — not just code that looks right?
Location: Remote / Canada-friendly
Duration: 3–6 months (flexible)
Compensation: Paid
About the Role
We are looking for a sharp Machine Learning Intern at the intersection of AI systems (LLMs, RAG) and digital hardware design.
You will work on applying retrieval-augmented generation (RAG) techniques to one of the hardest open problems in EDA: generating correct, synthesizable RTL from natural language and structured specifications.
This is a research-leaning engineering role. You will design and evaluate RAG pipelines, build domain-specific corpora, and measure correctness of generated hardware — from prompt to simulation.
Why This Problem is Hard
Before diving in, read our article on why AI coding assistants — as powerful as they are — fundamentally struggle with hardware design:
Software Optimization vs. Silicon: Why AI Coding Assistants Fall Short in Hardware Design (Link: https://www.linkedin.com/feed/update/urn:li:activity:7432972364650520576/ )
The core tension: Software bugs crash programs. Hardware bugs get etched into silicon.
The correctness bar is significantly higher, and the feedback loop is much slower. Understanding this distinction is central to this role.
What You'll Work On
- Design and evaluate RAG pipelines for RTL generation (Verilog/SystemVerilog)
- Build and curate hardware-specific knowledge bases (ISA specs, RTL snippets, design patterns)
- Evaluate generated RTL using simulation tools (e.g., Verilator)
- Experiment with retrieval strategies, chunking, embeddings, and re-ranking
- Analyze failure modes — where and why generated RTL breaks
What We’re Looking For
Must Have:
- Strong understanding of RAG systems (retrieval, chunking, embedding, re-ranking, generation)
- Hands-on experience building LLM pipelines (LangChain, LlamaIndex, custom, or equivalent)
- Proficiency in Python
- Familiarity with transformer models and prompt engineering
Good to Have:
- Basic knowledge of digital design (logic gates, flip-flops, FSMs, pipelines)
- Exposure to HDLs (Verilog or VHDL)
- Understanding of processor architecture (fetch, decode, execute, memory, writeback)
- Experience with simulation tools (Verilator, Icarus Verilog, or similar)
Mindset
- Curious about the intersection of AI and systems engineering
- Comfortable with ambiguity and open-ended problems
- Rigorous about evaluation — focused on correctness, not just outputs
Click on Apply to know more.