Website:
velaura.ai
Job details:
Company Description Velaura AI, Inc. (formerly Auradine) is a leader in ultra-low power compute solutions designed for data center, edge, and physical AI applications. Founded by experienced entrepreneurs and technologists, the company blends deep technical expertise, proven intellectual property, and advanced silicon innovation to build high-performance, energy-efficient systems. Headquartered in Silicon Valley, California, Velaura AI focuses on solving complex compute challenges while reducing power consumption at scale. Team members work on cutting-edge hardware and software that enable next-generation AI workloads. The company offers an environment where technical excellence, innovation, and collaboration drive meaningful impact in real-world AI deployments.
Role Description The Low Power Synthesis Expert will be responsible for driving power-aware logic synthesis flows for complex digital designs, ensuring optimal trade-offs among power, performance, and area. This full-time, on-site role is based in Bengaluru and involves close collaboration with RTL design, physical design, and verification teams. Day-to-day tasks include developing and refining low-power synthesis methodologies, configuring and running EDA tools, analyzing reports, and implementing optimizations such as clock gating, multi-Vt usage, and power domain strategies. The role also includes debugging synthesis issues, supporting timing closure, and contributing to design guidelines and best practices. The expert will participate in reviews, document flows, and provide technical guidance to peers to improve overall design quality and efficiency.
Qualifications
- Strong experience in logic synthesis and low-power design techniques, including power-aware constraints, clock gating, and multi-voltage/multi-power domain methodologies.
- Hands-on proficiency with industry-standard EDA tools for synthesis and power analysis (e.g., Synopsys Design Compiler/Power Compiler, Cadence Genus, PrimeTime-PX or equivalents).
- Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog or VHDL), timing concepts, and power-performance-area trade-offs.
- Experience collaborating with physical design teams, including familiarity with floorplanning impacts, UPF/CPF-based power intent, and signoff flows.
- Ability to analyze reports, debug complex design issues, and systematically optimize designs for power and timing closure.
- Strong communication and documentation skills, with the ability to work effectively in cross-functional teams and mentor less experienced engineers.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field; prior experience in advanced nodes and AI/accelerator designs is a plus.
- Comfort working on-site in Bengaluru, with a proactive approach to learning, problem-solving, and contributing to a fast-paced startup environment.
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