Job Summary
We are seeking an experienced Static Timing Analysis (STA) Engineer with strong expertise in timing closure, timing sign-off, and synthesis for advanced technology nodes. The ideal candidate should have hands-on experience in PrimeTime/Tempus, MMMC, timing constraints, and collaboration with Physical Design, DFT, RTL, and Design teams to achieve timing closure.
Key Responsibilities
- Perform block-level and SoC-level Static Timing Analysis (STA) and timing sign-off.
- Develop, validate, and maintain SDC timing constraints.
- Execute timing analysis across multiple modes and corners (MMMC).
- Drive setup and hold timing closure throughout the implementation flow.
- Perform timing ECOs and collaborate with Physical Design teams for closure.
- Analyze timing reports and identify critical timing paths.
- Work on clock tree analysis, clock uncertainty, and timing exceptions.
- Perform Lint, CDC, and timing constraint validation.
- Generate and validate SDF files for Gate-Level Simulations (GLS).
- Support IP and SoC integration teams with timing model generation (ETM/Liberty).
- Work closely with RTL, Design, DFT, and Verification teams to resolve timing issues.
- Ensure timing sign-off meets quality and tape-out requirements.
Mandatory Skills (Deal Breakers)
- 5+ years of hands-on experience in Static Timing Analysis.
- Strong expertise in Synopsys PrimeTime and/or Cadence Tempus.
- Experience with MMMC timing analysis and timing sign-off.
- Strong knowledge of SDC constraint development and debugging.
- Experience in Timing Closure (Setup/Hold).
- Hands-on experience in Synthesis using Synopsys Design Compiler or Fusion Compiler.
- Good understanding of Clock Tree Synthesis (CTS).
- Experience in Timing ECO implementation.
- Strong knowledge of SDF generation and Gate-Level Simulation support.
- Good understanding of DFT, Lint, and CDC.
- Experience with advanced technology nodes (28nm, 16nm, 7nm, 5nm, 3nm, or below).
Preferred Skills
- Experience with Fusion Compiler.
- Knowledge of UPF/Low Power timing analysis.
- Familiarity with SI-aware timing analysis.
- Experience with scripting using Tcl, Perl, Python, or Shell.
- Exposure to ETM/Liberty timing model generation.
- Knowledge of physical design flow and PnR concepts.
- Experience working on CPU, GPU, AI/ML, Networking, Automotive, or High-Speed Interface SoCs.
Required Tools
- Synopsys PrimeTime
- Cadence Tempus
- Synopsys Design Compiler / Fusion Compiler
- PrimeTime PX (preferred)
- VC SpyGlass (Lint/CDC) (preferred)
- Linux
- Tcl, Perl, Shell, or Python
Educational Qualification
- B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Electrical Engineering, or a related discipline.
Nice to Have
- Experience in advanced FinFET technology nodes (7nm/5nm/3nm).
- Experience in timing sign-off for full-chip or large SoCs.
- Strong debugging and problem-solving skills.
- Excellent communication and stakeholder management skills.
