We are looking for an experienced Standard Cell Circuit Design Engineer with over 10 years of industry experience in designing high-performance, low-power standard cell libraries for advanced technology nodes. The ideal candidate should possess strong expertise in transistor-level circuit design, characterization, library validation, and silicon debug while working closely with layout, CAD, PDK, and technology teams.
Key Responsibilities
- Design and develop high-performance, low-power, and area-optimized standard cell libraries for advanced technology nodes (3nm/5nm/7nm and below).
- Design combinational and sequential logic cells, clock gating cells, level shifters, isolation cells, retention cells, multi-bit flip-flops, and special-purpose cells.
- Perform transistor-level circuit design, optimization, and simulation using industry-standard EDA tools.
- Optimize cells for timing, leakage power, dynamic power, noise immunity, and reliability.
- Collaborate with layout engineers to achieve optimal layout quality while meeting DRC/LVS/ERC requirements.
- Drive characterization and validation of standard cell libraries across multiple PVT corners.
- Analyze and resolve issues related to signal integrity, variability, EM/IR, aging, and process variations.
- Support Liberty (.lib), LEF, GDSII, CDL, and SPICE model generation and validation.
- Work closely with CAD, PDK, characterization, and physical design teams for library integration and release.
- Participate in silicon bring-up, debugging, and correlation with simulation results.
- Mentor junior engineers and provide technical leadership across library development activities.
Required Skills
- 10+ years of experience in Standard Cell Circuit Design.
- Strong understanding of CMOS transistor-level circuit design.
- Expertise in Static and Dynamic Logic design methodologies.
- Experience designing:
- Standard Logic Cells
- Flip-Flops
- Latches
- Clock Gating Cells
- Multi-bit Flip-Flops
- Level Shifters
- Isolation Cells
- Retention Cells
- Clock Buffers and Inverters
- Strong knowledge of setup/hold timing, noise analysis, power optimization, and reliability.
- Experience with advanced FinFET technologies (3nm, 5nm, 7nm, 12nm).
- Expertise in SPICE simulations and transistor sizing.
- Experience with library characterization and validation flows.
- Good understanding of Liberty (.lib), LEF, GDSII, CDL, and Verilog models.
- Knowledge of EM/IR, ESD, Latch-up, Aging (BTI/HCI), and Process Variation analysis.
- Strong debugging and problem-solving skills.
Preferred EDA Tools
- Cadence Virtuoso
- Spectre
- Synopsys PrimeLib
- Synopsys Custom Compiler
- Liberate
- HSPICE
- FineSim
- Calibre DRC/LVS/PEX
- StarRC
- CustomSim
Preferred Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
- Experience with leading foundries such as TSMC, Samsung, Intel, or GlobalFoundries.
- Exposure to AI/HPC, CPU, GPU, Mobile, Networking, or Automotive SoC development is highly desirable.
- Strong communication, collaboration, and leadership skills.
Preferred Experience
- Standard Cell Library Development
- Library Characterization
- Circuit Verification
- Silicon Validation
- PPA (Power, Performance, Area) Optimization
- Advanced FinFET Technologies
- Variation-Aware Circuit Design
- Low-Power Circuit Design
