RTL Design Lead (Hands-on RTL Coding)
Job Summary
We are looking for an experienced RTL Design Lead with 10+ years of ASIC/SoC design experience who is passionate about hands-on RTL development. This role requires a strong technical leader who actively contributes to RTL coding, drives microarchitecture decisions, and owns the complete design cycle from specification to RTL sign-off.
The ideal candidate should have deep expertise in Verilog/SystemVerilog, digital design fundamentals, and ASIC design methodologies while collaborating closely with Verification, DFT, Physical Design, and Architecture teams.
Key Responsibilities
Own the RTL design and microarchitecture of complex ASIC/SoC IPs and subsystems.
Develop high-quality, synthesizable RTL using Verilog and SystemVerilog.
Translate architectural specifications into efficient RTL implementations.
Drive RTL quality through coding reviews, lint, CDC, and synthesis closure.
Analyze and resolve functional, timing, and design-related issues.
Work closely with Verification, DFT, Physical Design, and STA teams throughout the development cycle.
Review design specifications and provide technical recommendations.
Mentor junior engineers and establish RTL coding best practices.
Ensure timely delivery of high-quality RTL that meets performance, power, and area (PPA) goals.
Required Skills & Qualifications
Bachelor's or Master's degree in Electronics/Electrical Engineering or a related field.
10+ years of hands-on experience in ASIC/SoC RTL Design.
Strong expertise in Verilog and SystemVerilog.
Excellent RTL coding skills with recent hands-on development experience.
Strong understanding of digital design fundamentals, FSMs, pipelining, clock domain crossing, reset strategies, and synchronization techniques.
Experience in microarchitecture development and RTL implementation.
Hands-on experience with Lint, CDC, Synthesis, and Design Constraints (SDC).
Familiarity with ASIC design flow from specification through tape-out.
Strong debugging, analytical, and problem-solving skills.
Excellent communication and technical leadership abilities.
Preferred Skills
Experience with AMBA/AXI, PCIe, DDR, Ethernet, USB, or other high-speed protocols.
Exposure to Low Power Design (UPF), Formal Verification, and STA concepts.
Experience with Synopsys Design Compiler, SpyGlass, Primetime, or equivalent EDA tools.
Experience leading small RTL design teams while remaining an active individual contributor.
What We're Looking For
A technically strong RTL engineer who continues to write production-quality RTL code.
Someone who leads by example through technical excellence rather than only project management.
Passion for solving complex digital design challenges and delivering high-quality silicon.
Ability to mentor engineers while maintaining strong hands-on involvement in design activities.
Preferred Candidate
Experience: 10+ Years
Location: Bengaluru
Notice Period: Immediate to 15 Days Preferred