Senior Physical Design Engineer

LeadIC Design

Experience: 4+ yrs
Location: Bengaluru
Job type: Full-time

Required skills

physical design
Place and Route (PnR)
floorplanning

Nice to have

Innovus
low power design
Tempus

About the role

Senior Physical Design Engineer (4–10 Years)

LeadIC is looking for experienced Physical Design Engineers to join our growing VLSI team working on cutting-edge SoC designs across advanced technology nodes (16nm/7nm/5nm/3nm).

Responsibilities

Perform complete RTL-to-GDSII Physical Design implementation.
Execute Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
Drive Timing Closure, SI Closure, Power Optimization, and Area Optimization.
Perform MCMM timing analysis using PrimeTime.
Resolve DRC/LVS and physical signoff issues.
Implement ECOs and support tape-out activities.
Collaborate with RTL, DFT, STA, and Verification teams.
Develop TCL automation to improve design productivity.

Required Skills

4+ years of hands-on Physical Design experience.
Strong expertise in ICC2 and/or Fusion Compiler.
Experience with complete PnR flow.
Strong knowledge of STA using PrimeTime.
Hands-on experience with Floorplanning, CTS, Routing, Timing Closure, and Signoff.
Experience in advanced technology nodes (16nm/7nm/5nm/3nm).
Good understanding of IR Drop, EM, Crosstalk, and Low Power methodologies.
Strong TCL scripting skills.

Good to Have

Innovus, Tempus, Genus
RedHawk, StarRC, Calibre
Python/Shell scripting
UPF and Low Power Design
Hierarchical SoC implementation

Preferred Notice Period

Immediate to 30 Days

About LeadIC Design

Founded in 2018, LeadIC has evolved into a trusted partner for global semiconductor companies, supporting the complete chip development lifecycle with deep technical capability, strong execution ownership, and flexible engagement models. With engineering teams across India and Canada.

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