Role:* RTL Micro Architect Lead
*Location:* Onsite BLR
*Required Skills*
8+ years of experience in microarchitecture and RTL development for complex SoCs.
Strong expertise in Verilog/SystemVerilog and digital design methodologies.
Experience with GPU, DSP, image/video processing, AI/ML accelerators, or signal-processing architectures.
Solid understanding of SoC fabrics, memory hierarchies, cache/coherency concepts, and high-speed interfaces.
Proven leadership in driving design reviews, technical decisions, and cross-functional execution.
*Key Responsibilities:*
Define microarchitecture specifications for GPU, DSP, and signal-processing accelerators within complex SoCs.
Lead RTL design, implementation, integration, and performance optimization of subsystem blocks.
Drive architectural trade-off analysis across performance, power, area (PPA), and scalability objectives.
Develop and review design specifications, RTL code, and integration guidelines.
Collaborate with verification teams on test plans, coverage closure, and debug of pre/post-silicon issues.
Work with SoC, interconnect, memory, and firmware teams to ensure seamless subsystem integration.
Support timing closure, power optimization, and silicon bring-up activities.