Physical Design Engineer

Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.

· Should have experience on Physical Design Methodologies and lower tech nodes like 5nm & 3nm.

· Should have experience in handling high frequency partitions & memory dominated designs.

· Should have experience on programming in Tcl/Tk/Perl.

· Expertise on Flow development is a plus.

· Expertise on budgeting, full chip timing & Full chip PV is a plus.

· Expertise on Bump planning, RDL routing, ESD implementation is a plus.

· Well versed with timing constraints, STA, and timing closure.

· Should have experience in handling Full chip & hierarchical partitions.

· Should have worked on atleast 1 full chip tapeout.

· Tools: Innovus, Genus, Tempus & Calibre