Responsibilities will include, but not limited to:
· Good knowledge of Basic Analog/Digital concepts.
· Good knowledge of Verilog/SV concepts.
· Experience in using spice simulation and digital simulation tools like Virtuoso, primesim, Finseim, Hspice, Xcellium, Simvision, Waveview.
· Experience in understanding Spice simulation environment/Digital simulation environment, able to debug analog/digital design related issues.
· Work experience in co-sim simulation designs is a plus.
· Good scripting skills using perl, python is a plus.
· Must possess good communication skills and ability to work well in a team.