We are looking for an experienced Analog Layout Engineer with 4–10 years of hands-on experience in full-custom analog and mixed-signal layout design. The ideal candidate should have strong expertise in advanced process nodes, layout optimization, physical verification, and close collaboration with circuit designers to deliver high-quality silicon.
Key Responsibilities
- Develop high-quality full-custom layouts for analog and mixed-signal IPs from schematic to GDSII.
- Perform device matching, symmetry, common centroid, interdigitation, shielding, guard rings, and other analog layout techniques.
- Execute floorplanning, routing, and layout optimization for performance, area, and manufacturability.
- Ensure clean physical verification by resolving DRC, LVS, ERC, Antenna, Density, and Latch-up violations.
- Perform parasitic extraction and support post-layout simulation.
- Work closely with circuit designers to optimize layout for performance, matching, noise, and reliability.
- Support tape-out activities and silicon bring-up.
- Coordinate with PDK and CAD teams for process updates and methodology improvements.
- Mentor junior layout engineers and review layouts for quality and best practices.
Required Skills
- 4–10 years of experience in Analog Layout Design.
- Strong hands-on experience in full-custom analog and mixed-signal layout.
- Expertise in matching-sensitive layouts including common centroid, interdigitation, symmetry, shielding, and guard rings.
- Experience with advanced technology nodes such as TSMC 3nm, 5nm, 6nm, 7nm, or 12nm.
- Strong knowledge of DRC, LVS, ERC, Antenna, Density, and Latch-up verification.
- Experience with parasitic extraction and post-layout verification.
- Familiarity with ESD-aware layout practices and reliability considerations.
- Good understanding of analog circuit blocks such as PLL, LDO, ADC, DAC, Bandgap, SerDes, SRAM, IO, or PMIC.
- Ability to work independently and collaborate effectively with cross-functional teams.
Preferred EDA Tools
- Cadence Virtuoso Layout XL
- Calibre (DRC/LVS/PEX)
- Virtuoso ADE
- Assura (optional)
- StarRC or Quantus (preferred)
Preferred Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
- Experience with TSMC, Samsung, Intel, or GlobalFoundries technologies.
- Strong communication and problem-solving skills.
