Analog Layout Engineer
LeadIC is hiring experienced Analog Layout Engineers for opportunities in Bengaluru (India) and Germany.
Open Positions
Analog Layout Engineer – 5–8 years
Senior/Lead Analog Layout Engineer – 8+ years
Responsibilities
Develop custom Analog, Mixed-Signal, IO, or Memory layouts.
Collaborate with circuit design and verification teams.
Perform layout optimization and Physical Verification.
Resolve DRC, LVS, and ERC issues.
Deliver high-quality layouts using Cadence Virtuoso and Calibre.
Mandatory Skills
Strong Analog Custom Layout experience.
Hands-on experience with Cadence Virtuoso and Calibre.
Good understanding of DRC, LVS, ERC, and Physical Verification.
Location-Specific Requirements
Bengaluru
Experience with 40nm or higher technology nodes.
Experience in Analog, Mixed-Signal, IO, or Memory layouts.
FinFET experience is not mandatory.
Germany
Mandatory experience with TSMC FinFET technology nodes.
Strong experience in advanced-node Analog Custom Layout.
If you're passionate about solving complex layout challenges and working with global semiconductor customers, we'd love to hear from you.