Job Summary
We are looking for an experienced Analog Layout Engineer to design and implement high-performance analog and mixed-signal layouts for advanced technology nodes. The ideal candidate should have strong expertise in full-custom layout, layout optimization, physical verification, and silicon-proven design methodologies.
Key Responsibilities
- Design high-quality full-custom analog and mixed-signal layouts.
- Perform device matching, symmetry, common-centroid placement, shielding, and guard ring implementation.
- Execute floorplanning and optimize layouts for area, performance, reliability, and manufacturability.
- Perform DRC, LVS, ERC, and PEX closure using industry-standard verification tools.
- Work closely with Analog Design, CAD, Physical Verification, and Process teams.
- Resolve layout-related issues and support tape-out activities.
- Ensure layouts comply with process design rules and reliability requirements.
- Document layout methodologies and follow project timelines.
Mandatory Skills (Deal-Breakers)
Candidates must have the following skills:
- 4+ years of hands-on experience in Analog Layout.
- Strong expertise in full-custom analog layout.
- Experience with Cadence Virtuoso Layout XL/GXL.
- Excellent understanding of:
- Device matching techniques
- Common-centroid layout
- Interdigitation
- Symmetry
- Guard rings
- Shielding
- Dummy devices
- Experience with DRC, LVS, ERC, and PEX closure.
- Hands-on experience using Calibre or Cadence Pegasus for physical verification.
- Good knowledge of advanced technology nodes such as 2nm, 3nm, 5nm, 7nm, 12nm, 16nm, or FinFET technologies.
- Understanding of electromigration (EM), IR drop, latch-up, ESD, and reliability guidelines.
- Experience in complete layout ownership from block level through tape-out.
- Strong debugging and problem-solving skills.
Good-to-Have Skills
- Experience with SerDes, PLL, ADC, DAC, Bandgap, LDO, PMIC, Memory, or High-Speed Interfaces.
- Exposure to Custom Compiler or other custom layout environments.
- Experience with EM/IR analysis tools.
- Knowledge of FinFET and advanced process design methodologies.
- Scripting knowledge in Skill, Python, Perl, or TCL.
- Experience in automotive or high-reliability semiconductor products.
- Familiarity with low-power design techniques.
- Exposure to package-aware layout considerations.
- Experience working in multi-site/global engineering teams.
- Prior silicon bring-up or post-silicon support experience.
