ACL Digital
Website:
acldigital.com
Job details:
Job Title: STA (Static Timing Analysis) Engineer
Company: ACL Digital
Locations: Bengaluru & Hyderabad
Experience: 8+ Years
Industry: Semiconductor / VLSI Design
Job Summary:
ACL Digital is hiring an experienced STA Engineer with strong expertise in timing analysis and signoff for complex SoCs. The ideal candidate should have hands-on experience with industry-standard timing tools like Cadence Tempus and Synopsys PrimeTime, and a deep understanding of timing closure methodologies.
Key Responsibilities:
- Perform block-level and full-chip STA across all PVT corners and modes
- Drive timing closure for setup, hold, recovery, and removal checks
- Work extensively with:
- Cadence Tempus
- Synopsys PrimeTime
- Analyze and debug timing violations and provide ECO solutions
- Handle constraints development and validation (SDC)
- Perform clock path analysis including skew, latency, and uncertainty
- Work closely with Physical Design, RTL, and DFT teams for timing convergence
- Support signoff activities including SI, noise, and variation analysis
Required Skills:
- Strong expertise in Static Timing Analysis (STA) methodologies
- Hands-on experience with:
- Cadence Tempus
- Synopsys PrimeTime
- Deep understanding of:
- Timing constraints (SDC)
- Multi-mode multi-corner (MMMC) analysis
- OCV/AOCV/POCV concepts
- Experience in timing closure at block and full-chip level
- Knowledge of low-power intent (UPF/CPF is a plus)
- Scripting skills (TCL, Perl, or Python)
Click on Apply to know more.