Website:
bestnanotech.in
Job details:
Lead / Senior Design Verification Engineer (SoC) — 7+ Years
Location: Pune, India
Experience: 7+ years (relevant SoC DV)
Role Summary
Own and drive
SoC Design Verification for complex IP/subsystem/SoC programs. You will manage verification execution, build scalable verification environments, and ensure closure on coverage, assertions, and quality targets for both
high-speed and
low-speed interfaces.
Key Responsibilities
- Lead end-to-end SoC verification execution: verification strategy, planning, schedules, and closure.
- Develop verification plans, test plans, and reusable SystemVerilog/UVM testbenches.
- Verify high-speed and low-speed interfaces including: I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, HBM.
- Implement and review SystemVerilog Assertions (SVA) and functional coverage models.
- Drive coverage closure: code, toggle, and functional coverage; identify gaps and improve tests.
- Debug complex failures, analyze regressions, and work closely with design/architecture teams to resolve issues.
- Integrate and validate third-party VIPs (Synopsys/Cadence) and maintain VIP-based verification flows.
- Run and triage regressions, improve efficiency, and ensure consistent delivery against milestones.
- (Optional/Added advantage) Perform Gate-Level Simulation (GLS) and power-aware verification.
Must-Have / Non-Negotiable Skills (Top 10)
Use these in the LinkedIn job “Skills” section for tighter AI matching:
- SoC Design Verification ownership (planning → execution → closure)
- SystemVerilog (SV) proficiency for verification
- UVM-based testbench development and reuse
- SVA (SystemVerilog Assertions) writing and debug
- Coverage expertise: functional + code/toggle coverage and closure
- Protocol verification experience across peripherals: I2C/I3C, SPI, UART, GPIO, QSPI
- High-speed protocol verification exposure: PCIe / Ethernet / CXL / MIPI / DDR / HBM (at least 2–3 in depth)
- Synopsys VCS (simulation/regressions/debug)
- Cadence Xcelium (Xsim) (simulation/regressions/debug)
- VIP integration (Synopsys and/or Cadence Verification IP)
Good-to-Have (Added Advantage)
- Gate-Level Simulations (GLS) experience
- Power-aware verification using UPF and X-propagation (Xprop)
- Experience managing larger regression farms, test planning for multi-IP SoCs, or subsystem integration DV
Education
- B.E./B.Tech/M.E./M.Tech in Electronics/Electrical/Computer Engineering (or equivalent)
Click on Apply to know more.