Website:
anthriq.com
Job details:
About the Role
We are building a high-performance signal processing ASIC — a multi-core vector processor with a custom ISA, targeting defense, 5G, and test & measurement markets. You will lead the RTL implementation from architecture spec to tapeout-ready netlist. This is a hands-on technical lead role. You write RTL, review RTL, and own the synthesis flow. You are the bridge between the architect (who defines the spec) and the RTL team (who implements it).
Responsibilities
- Translate the architecture specification into synthesizable SystemVerilog
- Own the RTL coding standards, linting rules, and design methodology
- Lead a team of 5-7 RTL engineers through the full design cycle
- Own the synthesis flow (Design Compiler or Genus) and drive timing closure
- Define and maintain SDC timing constraints
- Review all RTL code submissions for correctness, synthesizability, and style
- Coordinate with the outsource partner on GDSII hando (netlist, constraints, floorplan guidance)
- Work closely with the verification team to resolve bugs and achieve coverage closure
Requirements
- 8+ years of RTL design experience in SystemVerilog
- At least 1 tapeout through to GDSII (not just RTL — you've seen the full flow)
- Synthesis and timing closure experience (Design Compiler or Genus, PrimeTime or Tempus)
- Processor, DSP, or datapath-heavy design experience
- Familiarity with advanced process nodes (28nm class or below)
- Strong code review skills, you can spot timing hazards, FSM issues, and non-synthesizable patterns in review
- Comfortable leading a small team while remaining hands-on
Nice to Have
- VLIW or vector processor design experience
- Experience with deterministic/real-time architectures (no caches, fixed latencies)
- Formal verification awareness (writing SVA, working with formal tools)
- FPGA prototyping experience (Vivado)
Click on Apply to know more.