Lead FPGA Design Engineer

Website: anthriq.com
Job details:

As part of our mission to build cutting-edge mixed-signal systems, we are seeking a Lead FPGA Design Engineer to own the architecture and implementation of performance-critical, production-grade FPGA designs on Xilinx platforms.

This role is ideal for someone with deep expertise in RTL design, FPGA implementation flows, AXI-based system integration, and hardware bring-up, who thrives at the intersection of digital design, embedded systems, and real-time signal processing.

Role Overview

As Lead FPGA Design Engineer, you will architect, implement, and optimize the full FPGA design stack from RTL coding and IP integration to synthesis, timing closure, and hardware validation. You will work across:

• RTL design and verification (VHDL / Verilog)
• AXI-based system interconnects and IP integration
• FPGA synthesis, implementation, and timing closure
• Mixed-signal interfaces and high-speed serial protocols
• Embedded processor subsystems (MicroBlaze / RISC-V)
• FPGA bring-up, hardware debugging, and signal analysis

You will provide strong technical leadership, mentor the FPGA engineering team, and collaborate closely with hardware, embedded software, systems, and DSP teams.

Key Responsibilities

1. FPGA Architecture & System Design

• Architect modular, reusable FPGA design frameworks targeting Xilinx UltraScale+, Versal, and Zynq MPSoC platforms
• Define top-level FPGA architecture, including partitioning, clocking strategy, and interface hierarchy
• Make critical design decisions balancing latency, throughput, resource utilization, and power
• Drive Partial Reconfiguration (PR) and Dynamic Function eXchange (DFX) strategies where applicable
• Own the FPGA design database, release process, and version-controlled design environment

2. RTL Design & Implementation — Core Mandate

RTL ownership is a non-negotiable expectation of this role.

• Design and develop production-quality RTL in VHDL and/or Verilog for complex FPGA designs
• Define and enforce RTL coding standards, review guidelines, and reuse methodologies across the team
• Implement and optimize:
• AXI4 / AXI4-Lite / AXI4-Stream interfaces and interconnect fabrics
• Custom IP cores and Xilinx catalog IP integration
• MicroBlaze RISC-V processor subsystems
• DSP blocks, FIFOs, state machines, and control logic
• Manage CDC (Clock Domain Crossing) strategies and reset architectures across multi-clock designs
• Execute synthesis and implementation in Vivado, driving timing closure on complex, multi-constraint designs

3. I/O Planning, Constraints & Timing Closure

• Lead I/O planning, pinout definition, and package-level resource allocation for high-density FPGA designs
• Define and manage XDC constraints: timing, placement, I/O standards, and physical implementation directives
• Drive timing closure through floorplanning, pipelining, and logic restructuring
• Optimize designs for performance, power, and resource utilization across implementation runs

4. Hardware Bring-Up & Debugging

• Lead FPGA bring-up on target hardware; serve as the primary technical escalation point during board bring-up
• Debug complex FPGA designs using ILA, ChipScope, JTAG, and logic analyzers
• Collaborate with PCB/hardware teams on signal integrity, power delivery, and mixed-signal interface validation
• Integrate and validate JESD204B/C, PCIe, Ethernet, and other high-speed serial interfaces

5. Verification & Validation

• Define verification strategies, simulation environments, and sign-off criteria for functional validation
• Review and guide the development of VHDL/Verilog test benches for unit and integration-level testing
• Apply formal verification or advanced simulation methodologies where applicable
• Document design specifications, implementation details, and test results to production-grade standards

6. Leadership & Mentorship

• Mentor junior and mid-level FPGA engineers; conduct thorough RTL and design reviews
• Define engineering standards, best practices, and system-level design documentation
• Serve as technical point of contact in cross-functional discussions with hardware, software, and systems teams — and external stakeholders where required
• Present architecture proposals and design reviews to management and customers; strong communication skills are essential
• Participate in hiring, technical interviews, and team growth planning
• Drive project planning, effort estimation, and technical risk assessment

7. Research & Technology Alignment

• Evaluate emerging Xilinx/AMD platforms, tools, and IP and make adoption recommendations
• Stay current with advances in FPGA architecture, high-speed design, and real-time signal processing
• Translate DSP algorithm and systems research into efficient, timing-closed FPGA implementations
• Contribute to automation using TCL and/or Python scripting for design flow and tool integration

Requirements

Education

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• Master's degree preferred

Experience

• 7–10 years of hands-on FPGA design and implementation experience on Xilinx platforms
• Proven track record delivering production-grade RTL for complex, timing-critical FPGA designs
• Demonstrated experience leading FPGA projects from architecture through bring-up and validation

Core Technical Skills

• Expert RTL design in VHDL and/or Verilog — MANDATORY:
• Production-quality coding practices, peer review, and reuse methodology
• CDC analysis, reset strategy, and multi-clock domain design
• AXI4 / AXI4-Lite / AXI4-Stream interface design and integration
• Deep proficiency with Vivado Design Suite:
• Synthesis, implementation, and advanced timing closure
• XDC constraint management, floorplanning, and physical optimization
• Hands-on experience with FPGA bring-up and hardware debugging (ILA, ChipScope, JTAG)
• Experience with MicroBlaze RISC-V processor subsystem implementation and integration
• Strong expertise in IP core development and Xilinx catalog IP customization
• Experience with mixed-signal designs and high-speed serial interfaces
• Strong debugging and problem-solving skills for complex FPGA designs

Bonus / Good to Have

• Experience with specific Xilinx device families: UltraScale+, Versal, or Zynq MPSoC
• JESD204B/C interface design and validation experience
• Knowledge of high-speed serial protocols: PCIe, Ethernet, Aurora
• Partial Reconfiguration (PR) and Dynamic Function eXchange (DFX)
• DSP concepts and FPGA-based signal processing implementations
• Embedded software development for FPGA-based systems
• Formal verification or advanced simulation methodologies
• Proficiency in Python and/or TCL for design automation and CI/CD integration
• Experience in agile or scrum-based development environments
• Prior experience in a formal technical lead or team lead capacity

Soft Skills

• Strong systems thinking with the ability to navigate large, complex FPGA architectures
• Exceptional problem-solving under tight timing and resource constraints
• Cross-functional collaboration with hardware, embedded software, DSP, and systems teams
• Excellent communicator who documents clearly, presents confidently, and leads by example
• Ability to make and defend architectural decisions under ambiguity and project pressure

What We Offer

• Competitive salary and comprehensive benefits package commensurate with lead-level experience
• Opportunity to shape the architecture of cutting-edge FPGA designs and technologies
• Leadership visibility with direct influence on team direction and technical strategy
• Professional development, conference participation, and training opportunities
• Collaborative and innovation-driven work environment
• Flexible work arrangements

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