Job Description: Formal Verification Engineer Job Title: Formal Verification Engineer Experience: 3+ Years Location: Bangalore, India Employment Type: Full-Time CTC: As per industry standards ABOUT THE ROLE We are looking for a talented Formal Verification Engineer to join our SOC design team. In this role, you will drive the correctness and reliability of complex silicon designs using state of-the-art formal methods, working closely with RTL designers, DV engineers, and architects across the full chip development lifecycle. KEY RESPONSIBILITIES ▪ Develop and maintain formal property checks (assertions, assumptions, covers) for SOC blocks including interconnects, memory subsystems, power management, and security IPs. ▪ Perform block- and chip-level formal verification using industry-standard tools (Cadence JasperGold, Synopsys VC Formal, or equivalent). ▪ Collaborate with RTL designers to close coverage, debug counterexamples, and sign off on verified functionality. ▪ Define and enforce formal verification methodology, guidelines, and reuse strategies across the project. ▪ Contribute to verification planning, closure tracking, and sign-off criteria for tape-out. ▪ Identify and resolve RTL design issues through formal analysis and root-cause debugging. ▪ Drive adoption of FPV, SEC (Sequential Equivalence Checking), and connectivity checks within the team. ▪ Own CDC (Clock Domain Crossing) verification — identify missing or incorrect synchronizers, detect multi-bit bus crossings, and formally prove absence of metastability-prone paths using CDC apps. ▪ Own RDC (Reset Domain Crossing) verification — ensure proper reset synchronization, correct deassertion sequencing across reset domains, and absence of glitches or X propagation at reset boundaries. • CDC & RDC VERIFICATION • CDC and RDC sign-off are first-class responsibilities in this role. The engineer is expected to: ▪ Perform structural and formal CDC analysis to verify synchronizer presence, convergence, and reconvergence across all asynchronous clock domain crossings. ▪ Verify multi-bit CDC paths using gray coding, handshake protocols, or async FIFOs; formally prove protocol correctness. ▪ Perform RDC analysis to ensure all resets are properly synchronized, deassertion is glitch free, and reset sequencing between domains is functionally correct. ▪ Detect and resolve reset domain violations — including cascaded reset issues, poweron reset interactions, and domain-specific reset trees. ▪ Use tools such as Synopsys SpyGlass CDC/RDC, Cadence JasperGold CDC, or equivalent for automated sign-off. ▪ Define and document CDC/RDC waivers with clear justification; track them to closure at tape-out. • REQUIRED QUALIFICATIONS ▪ 3–8 years of experience in formal verification of digital hardware designs. ▪ Proficiency in SystemVerilog Assertions (SVA) and property specification languages. ▪ Hands-on experience with at least one commercial formal verification tool (JasperGold, VC Formal, Questa Formal, etc.). ▪ Demonstrated experience in CDC verification — synchronizer types (2FF, handshake, async FIFO), reconvergence analysis, and formal CDC apps. ▪ Demonstrated experience in RDC verification — reset synchronizer design, deassertion sequencing, and reset domain isolation checks. ▪ Solid understanding of RTL design concepts, digital logic, and SOC architectures. ▪ Experience working with AXI, AHB, APB, or other standard bus protocols. ▪ Strong debugging skills and ability to interpret and resolve formal counterexamples. ▪ B.E./B.Tech or M.Tech in Electronics, Electrical Engineering, or related field.