- Salary
- ₹6 - 20 LPA
- Experience
- 5+ yrs
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- Automatic Test Pattern Generation - ATPG
- Scan Insertion
About the role
Title: DFT Verification Engineer
Experience: 5-8 Years
Job Summary:
We are looking for a skilled DFT Verification Engineer to join our VLSI design team. The ideal candidate will be responsible for verifying DFT logic including scan, BIST, JTAG, and boundary scan verification on complex SoC designs, ensuring high fault coverage and silicon quality.
Key Responsibilities:
- Perform functional verification of DFT logic (scan chains, ATPG, test control logic, TAP controller, boundary scan) using simulation
- Collaborate with design and DFT implementation teams to review and verify DFT architecture and netlist
- Validate scan compression, X-masking, and clock domain constraints
- Perform gate-level simulation (GLS) with SDF back-annotation to verify timing and DFT correctness
- Debug DFT-related failures and work with cross-functional teams for root cause analysis
- Review and sign off on DFT verification closure metrics including fault coverage and chain continuity
Required Skills & Qualifications:
- B.E./B.Tech or M.Tech in Electronics / VLSI / Computer Engineering
- 5-8 years of hands-on experience in DFT verification
- Strong knowledge of scan architecture, ATPG, MBIST, JTAG (IEEE 1149.1), and boundary scan
- Proficiency with industry-standard EDA tools: Synopsys Tessent / TetraMAX, Mentor ATPG
- Experience with HDL simulation using VCS, Xcelium, or Questa
- Good understanding of STA constraints and their impact on DFT
- Familiarity with UVM/OVM-based verification methodologies is a plus
- Experience with Perl/Python/Shell scripting for verification automation |
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