FPGA Designer

Responsibilities
As FPGA Designer, you will be responsible for the definition and development of complex FPGA designs for protocol test (for ex PCIe, CXL, etc) and work in a highly collaborative, fast-paced environment. You will work closely with R&D Project Manager, Product Architects, Solution Teams, Software Qualification and Software Engineers to develop new product offerings and improve existing ones. The candidate should be a strong team worker and should be able and willing to collaborate with other design teams located in US & Europe.

If you are passionate about pushing the boundaries of technology and thrive in a collaborative and fast-paced environment, we invite you to join our team and contribute to the advancement of PCIe solutions.

The candidate will work closely with teams in Germany and US and coordinate with partners who provide R&D resources necessary for executing the project.

Qualifications
Education:

Bachelor degree or Master degree in Electronics/ Electrical Engineering with 14 to 18+ years of experience.
Essential:

Develop and maintain FPGA designs using hardware description languages (HDLs) such as VHDL or Verilog, ensuring they meet the functional and performance requirements.
We seek candidates who have experience working on large, complex designs within multiple developer environments. This includes collaborating with cross-functional teams, managing dependencies, and ensuring seamless integration across different work streams.
Collaborate with system architects to define the system architecture and determine how the FPGA will interface with other components on the PCA board and choose an appropriate FPGA based on the project's requirements.
Use FPGA development tools to synthesize and implement the design onto the FPGA, considering resource utilization and timing constraints.
Experience of Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. 
Experience with digital signal processing (DSP) and high-speed communication protocols.
Experience with timing closure for complex designs 
Experience of Functional Simulation tools – Synopsys or Mentor or Cadence or Vivado simulator 
Experience of creating self-checking Simulation environment involving test bench, scripts for automation, writing test cases. 
Excellent communication skills both verbal & written
Preferred:

Experience with high data throughput realtime processing (~ 1GSPS), PCIe, USB , DDR etc
Experience using Test & Measurement lab equipment. 
Knowledge of C/C++
Familiarity with Microsoft Visual Studio
Familiarity with Atlassian tools – Confluence, Jira, Bitbucket