RTL Design Engineer
KeenSemi
- Experience
- 3+ yrs
- Location
- Bengaluru
- Job type
- Full-time
Nice to have
- RTL Design (Verilog/SystemVerilog)
- Lint / CDC / UPF
- IP/SoC Integration
About the role
- Bachelor's degree in Electrical Engineering, Electronics Engineering or a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog, VHDL or SystemVerilog.
- Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
- Experience in Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) quality checks.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
- Experience in IP/Subsystem integration in SOC
- Good knowledge on Unit level testing and verification techniques
- Good knowledge on AMBA protocols, UART/I2C/SPI/I2S/Timers IPs
- Participate in test plan and coverage analysis of the block and ASIC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
About KeenSemi
KeenHeads is a semiconductor design services company providing turnkey and augmentation solutions for IP, SoC, ASIC, and FPGA development. We deliver specification-to-package ASIC solutions, partnering with clients to drive innovation, quality, engineering excellence, and growth.
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