Role : Lead the RTL-to-GDSII flow, ECO implementation, physical verification (DRC/LVS), and design optimization while collaborating with cross-functional teams. Driving innovation in VLSI methodologies, mentoring engineers, and staying updated with industry advancements. Enhancing efficiency and performance for team.
Desired Skills
Apply AI/ML techniques to optimize floorplanning, placement, CTS, and routing for improved PPA.
Develop and integrate AI-driven flows for timing closure, congestion reduction, and ECO automation.
RTL to GDSII Flow: Proven ability to manage and execute the entire physical design flow, ensuring efficient and high-quality project completion.
ECO Implementation: Strong experience in Engineering Change Order (ECO) execution, optimizing designs as per evolving requirements.
Physical Verification: Mastery of Design Rule Checking (DRC) and Layout Versus Schematic (LVS) to ensure design integrity and manufacturability.
EDA Tool Expertise, Synopsys IC Compiler, Fusion Complier, Innovus: Skilled in utilizing its advanced features for effective place-and-route strategies. Proficient in optimizing physical design workflows using its capabilities.
Strong analytical ability to fine tune constraints and ensure design timing closure.
Familiarity with DFT methodologies to improve post-production testing and validation.
Ability to manage multiple engineers on project.
Ability to converge timing using primetime / tempus
Managing & Reporting Schedule and Status of deliverables
Clarity in Communication
Scripting and Automation skills