VHDL/FPGA Design Engineer

Designing High Performance digital blocks for Complex Communication Codingusing VHDL. Hands-on with RTL development (VHDL), simulation, writing test benches, anddebug. Experience with developing timing constraints and running state-of-the-artsynthesis tools, timing analysis tools, such as Xilinx Vivado suite. Participate in module architecture and specification. Block level design verification Strong hands-on with RTL development (VHDL), simulation, writing test benches, and debug. Experience with developing timing constraints and running state-of-the-artsynthesis tools, timing analysis tools, such as Xilinx Vivado suite. Must have worked on top level SoC integrated processor cores with standardperipherals. Must have exposure to communication protocols. Should be very good in the debugging the HDL codes, and be able to make progressby identifying and fixing the issues/bugs in the design. Good knowledge in SoC architecture, such as Xilinx Zynq SoC.