- Experience
- 2+ yrs
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- SpyGlass Lint
- CDC
- Synopsys Design Compiler (DC)
Nice to have
- timing constraints (SDC)
- Verilog
- Verdi
About the role
Mandatory Skills
- Strong experience in SoC Block Integration.
- Hands-on experience with SpyGlass Lint, CDC, Synopsys Design Compiler (DC), and VCLP.
- Good understanding of RTL synthesis and timing constraints (SDC).
- Strong coding skills in Verilog/SystemVerilog/VHDL.
- Experience with Verdi or equivalent RTL debugging tools.
- Ability to collaborate with Verification, Physical Design, and DFT teams.
- Strong debugging, analytical, and problem-solving skills.
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