Job Responsibilities
Perform end-to-end ASIC Physical Design implementation.
Execute Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), and Routing.
Drive timing, power, congestion, and area optimization.
Perform physical verification and support design closure.
Collaborate with STA, DFT, and design teams to resolve implementation issues.
Required Skills
2–5 years of experience in ASIC Physical Design / Place & Route.
Hands-on experience in:
Floorplanning
Power Planning
Placement
CTS (Clock Tree Synthesis)
Routing
Strong understanding of physical design flow and timing closure.
Experience with Cadence Innovus and/or Synopsys ICC2.
Good to Have
TCL, Perl, or Python scripting.
Exposure to EMIR concepts.
