- Experience
- 2+ yrs
- Location
- Bengaluru
- Job type
- Full-time
Required skills
- SoC Integration Engineer
- Verilog
- SpyGlass
Nice to have
- CDC
- Synopsys Design Compiler
About the role
Mandatory Skills
- Strong experience in SoC Block Integration and RTL integration flow
- Hands-on experience with SpyGlass Lint
- Experience in Clock Domain Crossing (CDC) analysis and debugging
- Hands-on experience with Synopsys Design Compiler (DC) for RTL synthesis
- Experience with VCLP (Verification-Constraint-Lint-Power) flow
- Strong coding skills in Verilog/SystemVerilog (VHDL is an added advantage)
- Good understanding of SDC (Synopsys Design Constraints) and constraint management
- Experience with Verdi or equivalent RTL debugging tools
- Good understanding of ASIC/SoC design and implementation flow
- Ability to support Design Verification, Physical Design, and DFT teams
- Strong debugging, timing analysis, and problem-solving skills
- Good communication and cross-functional collaboration skills
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