- Salary
- $120k - $243k
- Experience
- 5+ yrs
- Location
- Roseville, California, United States
- Job type
- Full-time
Required skills
- SystemVerilog
- UVM
- Cadence Xcelium
- Synopsys VCS
- Mentor Questa
- Jenkins
- UPF
About the role
Requires 5+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
About Hewlett Packard Enterprise
Providing global edge-to-cloud infrastructure and IT solutions for businesses.
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