Website:
chipforge.ai
Job details:
Company Description Chipforge.ai is an AI-native chip design platform focused on the FPGA-first era, helping teams move from concept to working silicon with reduced time, cost, and specialist headcount. The platform integrates AI agents with modern EDA tools to automate key stages of RTL, verification, and physical design, so engineers can focus on high-impact problems. Built for high-trust and security-conscious environments, Chipforge.ai supports fully air-gapped deployments for sensitive and sovereign programs. With offices in Australia and Singapore, the company is designed for sovereign deployment from the outset and driven by a team with deep experience in overcoming the constraints of legacy chip design tools. Applicants will join an organization that is rethinking how advanced chips are designed and verified using AI automation.
Role Description As a Hardware Design Engineer (IP & Verification) at Chipforge.ai, you will design, implement, and verify digital hardware IP blocks that integrate into FPGA and ASIC workflows.
You will be:
- designing and verifying digital RTL IP in Verilog & SystemVerilog for FPGA-targeted (and ASIC-portable) flows.
- Owning and growing a library of synthesisable reference IP across major FPGA families, ensuring designs close timing and flow cleanly end-to-end through the Chipforge platform
- Building robust verification collateral — testbenches, assertions, and coverage models — that plugs directly into our tools and supports AI-driven self-correction in the design loop
- Creating a demonstrator designs like small CNN or transformer accelerators, RISC-V soft-core wrappers with peripherals, sensor-fusion data paths or industrial-control blocks which runs on real FPGA hardware that prove the platform from RTL all the way to bitstream
On a typical day, you will design digital IP blocks like accelerators, bus and interconnect controllers, peripheral cores and configurable wrappers around third-party and open-source IP, create verification plans, and build testbenches and regression suites to validate functionality and performance. You will collaborate with the team to integrate IP into larger systems, debug issues across simulation and hardware, and provide feedback that improves internal tooling and AI-assisted design flows. Documentation of design intent, verification results, and interface specifications will be an important part of your responsibilities. This is a full-time, hybrid role based with a mix of on-site collaboration and some work-from-home flexibility.
Qualifications
- Strong foundation in Hardware Development and Hardware Design, with experience taking IP from specification through implementation and verification.
- Proficiency in Electronics Hardware Design and Circuit Design, including understanding of digital logic, timing, and hardware constraints.
- Experience with Hardware Architecture, including defining modular, reusable IP blocks and system-level interfaces.
- Hands-on experience with RTL design and verification (e.g., Verilog/SystemVerilog, VHDL), including testbench creation, simulation, and coverage-driven verification.
- Familiarity with FPGA and/or ASIC design flows, EDA tools, and version control practices used in hardware development.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field, or equivalent practical experience.
- Ability to work effectively in a hybrid environment, collaborating in person and asynchronously with distributed teams.
- Strong analytical, problem-solving, and communication skills, with a focus on clear documentation and design review participation.
- Nice to have: experience with AI-assisted design tools, scripting for automation (e.g., Python, TCL).
Click on Apply to know more.