Proxelera
Website:
proxelera.com
Job details:
Job Summary:
We are looking for a highly skilled Full-Chip Static Timing Analysis (STA) Engineer with 3–6 years of experience in VLSI Physical Design/Timing Closure. The candidate will be responsible for full-chip timing analysis, timing closure, constraint development, and optimization activities across multiple design stages.
Key Responsibilities:
- Perform full-chip Static Timing Analysis (STA) and timing sign-off.
- Develop and validate SDC constraints.
- Handle timing closure activities including setup, hold, recovery, and removal checks.
- Analyze and resolve timing violations across different corners and modes.
- Work on MCMM (Multi-Corner Multi-Mode) timing analysis.
- Perform timing ECO implementation and validation.
- Collaborate with Physical Design, CTS, PnR, DFT, and RTL teams.
- Debug timing issues related to clock domains, false paths, and timing exceptions.
- Generate timing reports and provide design optimization recommendations.
- Support low-power timing verification activities.
Required Skills:
- Strong knowledge of STA concepts and timing sign-off methodology.
- Hands-on experience with:
- Synopsys PrimeTime
- Tempus (Cadence) – preferred
- TCL/Perl/Shell scripting
- Experience in:
- SDC constraints
- MCMM analysis
- Timing ECO
- OCV/AOCV/POCV concepts
- Crosstalk and SI analysis
- Clock Tree concepts
- Good understanding of VLSI design flow.
- Strong debugging and analytical skills.
Preferred Qualifications:
- B.Tech/M.Tech in Electronics / VLSI / ECE.
- Experience in advanced technology nodes (7nm/5nm/3nm preferred).
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