Genisup India Private Limited
Website:
genisup.com
Job details:
🚀 We’re Hiring: RTL Design & Verification Engineer!
📍 Bangalore, India
💼 Experience: 3–5 years
Are you passionate about memory-centric RTL design, SRAM integration, and building testchips that go all the way to silicon? Here’s your chance to work on next‑gen embedded memory technologies with a high‑impact team!
🔧
What You’ll Work On- RTL design for SRAM subsystems, wrappers, redundancy/ECC, access controllers
- Integration of SRAM, OTP/NVM memory IPs into SoCs & testchips
- Contribute to testchip development, bring‑up, and debug
- Drive micro‑architecture, specs, and technical reviews
- Own RTL quality: Lint, CDC/RDC, Synthesis QoR, Timing readiness
🧠
What You Bring- 3–5 years in Digital ASIC / RTL Design (Verilog/SystemVerilog)
- Strong experience integrating SRAM/memory IPs
- Solid grasp of clock/power domains, resets, SoC interfaces
- Experience with industry‑standard EDA tools
- Strong debugging, analysis, and problem‑solving skills
⭐ Bonus Skills
- Testchip experience or post‑silicon exposure
- MBIST, redundancy, or memory test modes
- UVM/SystemVerilog verification
- Scripting: Python/Perl/Tcl
If you enjoy working on challenging memory architectures, collaborating with compiler, DV, DFT & PD teams, and contributing to silicon that ships — we’d love to connect!
Click on Apply to know more.