UST
Website:
ust.com
Job details:
Job Title: FPGA Validation Engineer – SerDes
Experience: 5+ Years
Job Description:
We are seeking an experienced FPGA Validation Engineer with strong expertise in high‑speed SerDes interfaces to support validation, debug, and bring‑up of complex FPGA‑based systems. The role involves hands‑on validation at block and system level, close collaboration with design teams, and deep interaction with high‑speed protocols.
Key Responsibilities:
- Develop and execute FPGA validation test plans, test benches, and test cases at IP, subsystem, and system level.
- Perform bring‑up, validation, and debugging of FPGA designs on silicon/prototype boards.
- Validate and debug high‑speed SerDes interfaces (PCIe, Ethernet, JESD, USB, SATA, etc.).
- Use lab equipment such as high‑speed oscilloscopes, logic analyzers, BERTs, and protocol analyzers for issues isolation.
- Identify root causes of functional and signal‑integrity issues; work closely with design and board teams on fixes.
- Support timing closure, signal integrity checks, and performance validation for high‑speed designs.
- Create detailed validation reports and documentation.
Required Skills:
- Strong experience in FPGA validation and debug (Xilinx/AMD or Intel/Altera platforms).
- Hands‑on experience with SerDes PHYs and high‑speed protocols (PCIe, Ethernet, JESD204, USB, SATA, etc.).
- Proficiency in SystemVerilog / Verilog / VHDL for testbench development and debug.
- Experience with FPGA tools such as Vivado / Quartus, logic analyzers (ILA/SignalTap).
- Good understanding of clocking, reset, timing analysis, and CDC concepts.
- Strong debugging skills at RTL, gate‑level, and hardware level.
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