ACL Digital
Website:
acldigital.com
Job details:
Role : Senior FPGA Validation Engineer
Experience : 7+ years
Location : Hyderabad
--> Should have prior knowledge about SOC architecture, and emulation and prototyping platforms.
--> Opportunity to work in design verification, debug and system integration & work closely with the Architecture, Verification, ASIC Design and Software teams.
Responsibilities:
· Help set up FPGA/Emulation platform and device modeling
· Help set up FPGA/Emulation debugging tools
· Help customize the SOC design for the FPGA/Emulation platform
· Duties include modeling, debugging, creating and running validation tests, as well as supporting SW debugging
· Work with SOC design engineers, verification, systems and software team to achieve pre-silicon emulation and prototyping goals
Requirements:
· Strong experience working with FPGA and Emulation platforms. Familiarity with PCIe, USB, Ethernet, SPI and other commonly used protocols in SOC ASIC designs
· Strong experience working with FPGA tools likes Vivado
· Good knowledge of how FW/SW works on SOC
· Good communication skills
· BS or MS (preferred) degree in EE/EECS/CS or equivalent.
share cvs to divya.lakshmi@acldigital.com
Click on Apply to know more.