Tessolve
Website:
tessolve.com
Job details:
🚀 We're Hiring | Formal Verification Engineer | Tessolve Semiconductor
Are you passionate about Formal Verification and looking for your next opportunity?
Tessolve Semiconductor is hiring talented Formal Verification Engineers with 3+ years of experience.
Requirements:
✅ 3+ years of experience in Formal Verification
✅ Hands-on experience with SystemVerilog Assertions (SVA)
✅ Expertise in tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
✅ Strong understanding of RTL design (Verilog/SystemVerilog)
✅ Experience in property checking, equivalence checking, connectivity verification, and formal verification methodologies
📍 Location: Bengaluru / Hyderabad / Chennai
⏳ Notice Period: Immediate to 0–30 days preferred
If you're interested or know someone who would be a great fit, please share your updated resume at manjula.patil@tessolve.com.
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