ACL Digital
Website:
acldigital.com
Job details:
FPGA Design Engineers
Experience : 3-6 years
Location : Hyderabad
Looking for hands-on experience in Xilinx Vivado, RTL to bitstream flow, and strong digital design fundamentals (timing, CDC, AXI, SPI, I2C, UART).
Candidates with FPGA bring-up, debugging (ILA/Chipscope), and scripting (TCL/Python) skills are highly preferred.
📍 Location: Hyderabad | ⏳ Notice Period: 0–30 Days
📧 Apply now: janagaradha.n@acldigital.com
Click on Apply to know more.